MAX30101 Register Map

Map of MAX30101 I2C registers.

Author: Davide Marzorati

Defines

MAX30101_FIFO_CONF_REGISTER

FIFO Configuration register.

This register allows to configure the FIFO behaviour.

It is structured as follows:

B7	B6	B5	B4	B3	B2	B1	B0
SMP_AVG[2:0]	FIFO_ROL_LOVER_EN	FIFO_A_FULL[3:0]

Bits 7:5: Sample Averaging (SMP_AVE)

To reduce the amount of data throughput, adjacent samples (in each individual channel) can be averaged and decimated on the chip by setting this register.

SMP_AVG[2:0]	NO. OF SAMPLES AVG PER SAMPLE
000	1 (no averaging)
001	2
010	4
011	8
100	16
101	32
110	32
111	32

Bit 4: FIFO Rolls on Full (FIFO_ROLLOVER_EN)

This bit controls the behavior of the FIFO when the FIFO becomes completely filled with data. If FIFO_ROLLOVER_EN is set (1), the FIFO Address rolls over to zero and the FIFO continues to fill with new data. If the bit is not set (0), then the FIFO is not updated until FIFO_DATA is read or the WRITE/READ pointer positions are changed.

Bits 3:0: FIFO Almost Full Value (FIFO_A_FULL)

This register sets the number of data samples (3 bytes/sample) remaining in the FIFO when the interrupt is issued. For example, if this field is set to 0x0, the interrupt is issued when there is 0 data samples remaining in the FIFO (all 32 FIFO words have unread data). Furthermore, if this field is set to 0xF, the interrupt is issued when 15 data samples are remaining in the FIFO (17 FIFO data samples have unread data).

FIFO_A_FULL[3:0]	EMPTY DATA SAMPLES WHEN<br>INTERRUPT IS ISSUED	UNREAD DATA SAMPLES IN FIFO<br>WHEN INTERRUPT IS ISSUED
0x0h	0	32
0x1h	1	31
0x2h	2	30
0x3h	3	29
..	..	..
0xFh	15	17

MAX30101_MODE_CONF_REGISTER

MAX30101 Mode configuration register.

This register is structured as follows:

B7	B6	B5	B4	B3	B2	B1	B0
SHDN	RESET	-	-	-	MODE[2:0]

Bit 7: Shutdown Control (SHDN)

The part can be put into a power-save mode by setting this bit to one. While in power-save mode, all registers retain their values, and write/read operations function as normal. All interrupts are cleared to zero in this mode.

Bit 6: Reset Control (RESET)

When the RESET bit is set to one, all configuration, threshold, and data registers are reset to their power-on-state through a power-on reset. The RESET bit is cleared automatically back to zero after the reset sequence is completed. Note: Setting the RESET bit does not trigger a PWR_RDY interrupt event.

Bits 2:0: Mode Control

These bits set the operating state of the MAX30101. Changing modes does not change any other setting, nor does it erase any previously stored data inside the data registers.

MODE[2:0]	MODE	ACTIVE LED CHANNELS
000	Do not use
001	Do not use
010	Heart Rate mode	Red only
011	SpO2 mode	Red and IR
100-110	Do not use
111	Multi-LED mode	Green, RED, and/or IR

MAX30101_SPO2_CONF_REGISTER

Sp02 Configuration register.

This register configures the sensor for SpO2 mode.

It is structured as follows:

B7	B6	B5	B4	B3	B2	B1	B0
-	SPO2_ADC_RGE[1:0]	SPO2_SR[2:0]	LED_PW[1:0]

Bits 6:5: SpO2 ADC Range Control This register sets the SpO2 sensor ADC’s full-scale range:

SPO2_ADC_RGE[1:0]	LSB SIZE (pA)	FULL SCALE (nA)
00	7.81	2048
01	15.63	4096
02	31.25	8192
03	62.5	16384

Bits 4:2: SpO2 Sample Rate Control

These bits define the effective sampling rate with one sample consisting of one IR pulse/conversion, one RED pulse/ conversion, and one GREEN pulse/conversion. The sample rate and pulse-width are related in that the sample rate sets an upper bound on the pulse-width time. If the user selects a sample rate that is too high for the selected LED_PW setting, the highest possible sample rate is programmed instead into the register.

SPO2_SR[2:0]	SAMPLES PER SECOND
000	50
001	100
010	200
011	400
101	800
110	1600
111	3200

Bits 1:0: LED Pulse Width Control and ADC Resolution These bits set the LED pulse width (the IR, Red, and Green have the same pulse width), and, therefore, indirectly sets the integration time of the ADC in each sample. The ADC resolution is directly related to the integration time.

LED_PW[1:0]	PULSE WIDTH (uS)	ADC RESOLUTION (bits)
00	69 (68.95)	15
01	118 (117.78)	16
10	215 (215.44)	17
11	411 (410.75)	18

MAX30101_LED1_PA_REGISTER

MAX30101 LED1 Pulse Amplitude register.

This register allows to configure the pulse amplitude for LED1. The register is structured as follows:

B7	B6	B5	B4	B3	B2	B1	B0
LED1_PA[7:0]

The pulse amplitude is determined by the followint table:

LEDx_PA[7:0]	TYPICAL LED CURRENT (mA)
0x00h	0.0
0x01h	0.2
0x02h	0.4
…	…
0x0fh	3.0
…	…
0x1fh	6.2
…	…
0x3fh	12.6
…	…
0x7fh	25.4
…	…
0xFFh	51.0

MAX30101_LED2_PA_REGISTER

MAX30101 LED2 Pulse Amplitude register.

Please refer to led_pa for the configuration of this register.

MAX30101_LED3_PA_REGISTER

MAX30101 LED3 Pulse Amplitude register.

Please refer to led_pa for the configuration of this register.

MAX30101_LED4_PA_REGISTER

MAX30101 LED4 Pulse Amplitude register.

Please refer to led_pa for the configuration of this register.

MAX30101_MULTI_LED_1_REGISTER

MAX30101 Multi-LED Mode Configuration register - 1.

In multi-LED mode, each sample is split into up to four time slots, SLOT1 through SLOT4. #MAX30101_MULTI_LED_1 and #MAX30101_MULTI_LED_2 control registers determine which LED is active in each time slot, making for a very flexible configuration. Each slot generates a 3-byte output into the FIFO. One sample comprises all active slots, for example if SLOT1 and SLOT2 are non-zero, then one sample is 2 x 3 = 6 bytes. If SLOT1 through SLOT3 are all non-zero, then one sample is 3 x 3 = 9 bytes. The slots should be enabled in order (i.e., SLOT1 should not be disabled if SLOT2 or SLOT3 are enabled). Both LED3 and LED4 are wired to Green LED. Green LED sinks current out of #MAX30101_LED3_PA and #MAX30101_LED4_PA configuration in Multi-LED Mode and SLOTx[2:0] = 011.

The register is structured as follows:

B7	B6	B5	B4	B3	B2	B1	B0
-	SLOT2[2:0]	-	SLOT1[2:0]

The settings for #MAX30101_MULTI_LED_1 and #MAX30101_MULTI_LED_2 registers allows to setup the following Multi-LED modes:

SLOTx[2:0] Setting	WHICH LED IS ACTIVE	LED PULSE AMPLITUDE SETTING
000	None (time slot is disabled)	N/A (Off)
001	LED1 (RED)	#MAX30101_LED1_PA
010	LED2 (IR)	#MAX30101_LED2_PA
011*	LED3 (GREEN)	#MAX30101_LED3_PA[7:0]
LED4 (GREEN)	#MAX30101_LED4_PA[7:0]
100	None	N/A (Off)
101	RESERVED	RESERVED
110	RESERVED	RESERVED
111	RESERVED	RESERVED

MAX30101_MULTI_LED_2_REGISTER

MAX30101 Multi-LED Mode Configuration register - 2.

Please refer to #MAX30101_MULTI_LED_1 for the explanation of the register. The register is structured as follows:

B7	B6	B5	B4	B3	B2	B1	B0
-	SLOT2[2:0]	-	SLOT1[2:0]

MAX30101_TEMP_INT_REGISTER

MAX30101 Temperature Integer register.

The on-board temperature ADC output is split into two registers, one to store the integer temperature and one to store the fraction. * Both should be read when reading the temperature data, and the equation below shows how to add the two registers together: $T_{measured} = T_{integer} + T_{fraction}$ .

This register stores the integer temperature data in 2’s complement format, where each bit corresponds to 1°C.

B7	B6	B5	B4	B3	B2	B1	B0
TINT[7:0]

REGISTER VALUE (hex)	TEMPERATURE (°C)
0x00	0
0x01	+1
…	…
0x7e	+126
0x7f	+127
0x80	-128
0x81	-127
…	…
0xFE	-2
0xFF	-1

MAX30101_TEMP_FRACT_REGISTER

MAX30101 Temperature Fraction register.

This register stores the fractional temperature data in increments of 0.0625°C. If this fractional temperature is paired with a negative integer, it still adds as a positive fractional value (e.g., -128°C + 0.5°C = -127.5°C). This register is structured as follows:

B7	B6	B5	B4	B3	B2	B1	B0
-	-	-	-	TFRAC[3:0]

MAX30101_TEMP_CONF_REGISTER

MAX30101 Temperature Configuration register..

This register has only one bit which is used to trigger temperature measurements. This is a self-clearing bit which, when set, initiates a single temperature reading from the temperature sensor. This bit clears automatically back to zero at the conclusion of the temperature reading when the bit is set to one. This register is structured as follows:

B7	B6	B5	B4	B3	B2	B1	B0
-	-	-	-	-	-	-	TEMP_EN

MAX30101_REVISION_ID_REGISTER

MAX30101 Revision ID register.

This register holds the value for the revision ID number of the MAX30101.

MAX30101_PART_ID_REGISTER

MAX30101 Part ID Register.

This register holds the value for the revision ID number of the MAX30101: the expected value to be read is 0x15.